1. Field of the Invention
This application relates to co-pending application Ser. No. 08/224,820, filed the same day as this application, entitled ADDRESS SPACE CONVERSION TO RETAIN SOFTWARE COMPATIBILITY IN NEW ARCHITECTURES, by Larry Hewitt and Greg Smaus, which application is hereby incorporated by reference in its entirety.
2. Description of the Related Art
Many of today's multiprocessor computer systems utilize an interrupt scheme known as the advanced programmable interrupt controller (APIC). The APIC interrupt scheme allows hardware generated interrupts to be distributed to central processing units (CPUs) such that interrupts tend to avoid CPUs that are busy with higher priority tasks and interrupts tend to be assigned to CPUs that are involved in lower priority tasks. Also, the APIC interrupt approach allows CPUs to send interrupts to other CPUs via what is called an interprocessor interrupt (IPI). The APIC register set has become an industry-wide standard in the personal computer industry and is used by a large number of multiprocessing operating systems.
The APIC scheme includes two distinct interrupt controllers that typically reside on separate integrated circuits. One integrated circuit is called the input/output (I/O) APIC, which typically resides on the industry standard architecture (ISA) bus of a personal computer system. The second integrated circuit is the local integrated circuit or local APIC, which typically resides with each CPU either inside the CPU package or linked to the CPU via its host bus interface. Thus, there is one local APIC for each CPU in the system. The I/O APIC includes input pins that are driven by sources of hardware interrupts. The local APIC includes interrupt prioritization logic and methods for sending and receiving interrupts from external sources such as other local APICs or the I/O APIC.
A typical prior art APIC configuration is illustrated in FIG. 1. Each CPU 10, 12, 14, and 16 has a corresponding local APIC 11, 13, 15, and 17. The local APICs are all connected via APIC bus 20. Also attached to APIC bus 20 is I/O APIC 22 which is typically incorporated in an input/output integrated circuit 24.
The APIC bus 20 allows the various local APICs and the I/O APIC to communicate with each other. Thus, interrupts from, e.g., input/output devices received by the I/O APIC can be communicated to various of the local APICs and thus be serviced by one of the processors in the multiprocessor system. Prior art multiprocessor interrupt controller approaches are further described in U.S. Pat. No. 5,555,420 entitled "Multiprocessor Programmable Interrupt Controller System with Separate Interrupt Bus and Bus Retry Management" and U.S. Pat. No. 5,613,128 entitled "Programmable Multi-Processor Interrupt Controller System With a Processor Integrated Local Interrupt Controller," which patents are incorporated herein by reference.
The prior art interrupt controller approach, as illustrated in FIG. 1, has several disadvantages. If the local APIC is on the central processing unit integrated circuit as shown, for example, in FIG. 1, then the cost of providing the local APIC is high in terms of silicon real estate relative to other potential places in the system. On the other hand, if the local APIC is external to the CPU, but on the host bus, then an additional device must be added to the typical PC architecture. In a multiprocessor system, an additional integrated circuit must be included for each CPU in the system. Further, because the APIC bus is serial, there exists a latency from the time that the hardware interrupt is received on the I/O APIC and the time when that interrupt is transmitted to the local APIC via the serial bus. Further, the protocol for the serial bus is complex and difficult to design. Accordingly, it would be desirable to provide a simpler advanced programmable interrupt controller scheme for use in a multiprocessor environment that avoided expending costly CPU silicon area for interrupt controllers and also reduced latency in interrupt service.